Vertical semiconductor devices, in which a current flows between the electrodes on the major surfaces of a semiconductor chip, are widely used for power semiconductor devices. FIG. 36 is a cross sectional view of the active region, in which a main current flows, of a conventional planar-type n-channel vertical MOSFET. The conventional vertical MOSFET of FIG. 36 includes a drain electrode 20, an n+-type drain layer 11 with low electrical resistance in electrical contact with drain electrode 20, n−-type drift layer 12 working as a layer for sustaining a voltage on n+-type drain layer 11, p-type well regions 13 formed selectively in the surface portion of n−type drift layer 12, and an n+-type source region 15 formed selectively in the surface portion of p-type well regions 13.
A gate electrode 18 is above the extended portion of p-type well region 13 extended between n+-type source region 15 and the extended portion 14 of drift layer 12 extended between p-type well regions 13 with a gate insulation film 17 interposed therebetween. (Hereinafter, the extended portion 14 of drift layer 12 will be referred to as the “n−-type surface region 14”.) A source electrode 19 is in contact commonly with n+-type source regions 15 and p-type well regions 13.
A p+-type contact region 21 is formed in the surface portion of p-type well region 13. The p+-type contact region 21 is in contact with source electrode 19 to reduce the contact resistance between p-type well region 13 and source electrode 19 or to improve the latch-up withstanding capability.
An n-channel vertical IGBT is obtained by changing n+-type drain layer 11 in electrical contact with drain electrode 20 of the MOSFET in FIG. 36 to a p+-type drain layer with low electrical resistance. The upper structure including n−-type drift layer 12 working as a breakdown-voltage sustaining layer is the same with that of the MOSFET of FIG. 36. The IGBT works in the same manner as the MOSFET in the aspect that both the IGBT and the MOSFET feed signals to the respective gate electrodes to control the current flowing from the drain electrode to the source electrode. However, since the IGBT is a bipolar device while the MOSFET is a unipolar device, the voltage drop in the IGBT when the current is made to flow (in the ON-state) is small.
Although it is possible to express the on-resistance (voltage drop/current) in the ON-state of the vertical MOSFET or the IGBT by the total resistance of the current path inside the device, the resistance of the very resistive n−-type drift layer 12 occupies the most part of the total resistance of the MOSFET or the IGBT exhibiting a high breakdown voltage. In order to reduce the losses of the MOSFET and the IGBT, it is effective to reduce the specific resistance of n−-type drift layer 12 or to reduce the thickness of n−-type drift layer 12. However, since n−-type drift layer 12 is depleted in the OFF-state of the device such that n−-type drift layer 12 sustains the voltage, heavily doping n−-type drift layer 12 for reducing the specific resistance thereof or thinning n−-type drift layer 12 for reducing the resistance thereof causes a low breakdown voltage. Further, thickening of the n−-type drift layer 12 in order to obtain a semiconductor device with a high breakdown voltage, inevitably causes high on-resistance and high losses.
In short, there exists a tradeoff relation between the on-resistance and the breakdown voltage. It is well known that the tradeoff relation between the on-resistance and the breakdown voltage exists not only in the MOSFET's and the IGBT's but also in the other power semiconductor devices such as bipolar transistors and diodes, although its degree is different from device to device.
Since p-type well regions 13 are formed in the conventional semiconductor devices described above usually by introducing impurity ions through gate electrode layer 18 used as a mask, the planar pattern of p-type well regions 13 is an inversion of the planar pattern of gate electrode layer 18. FIG. 37 is a top plan view showing a planar arrangement pattern of the gate electrode in the conventional n-channel vertical MOSFET. FIG. 38 is a top plan view showing another planar arrangement pattern of the gate electrode in the conventional n-channel vertical MOSFET.
Referring now to FIG. 37, gate electrode 18 has square windows as disclosed in Japanese Examined Patent Application H07(1995)-83123. The p-type well regions 13 are square, since p-type well regions 13 are formed by introducing impurity ions through the windows of gate electrode 18. The n+-type source region is shaped with a square ring, since the n+-type source region is formed by introducing impurity ions through the window of gate electrode 18 used for defining the sides of the n+-type source region. In FIG. 37, contact regions 24 of the source electrode, formed in contact with p-type well regions 13 and n+-type source regions, are shown in the windows of the gate electrode. Contact region 24 has a square shape similar to that of p-type well region 13.
Referring now to FIG. 38, gate electrode 18 has hexagonal windows as disclosed in U.S. Pat. No. 4,593,302. In this case, p-type well regions 13 are hexagonal. Contact region 24 of the source electrode has a hexagonal shape similar to that of p-type well region 13.
MOS semiconductor devices include a breakdown withstanding structure usually formed around the active region thereof to sustain the breakdown voltage of the devices. A guard ring structure, a field plate structure or a combination of a resistive film and a field plate structure is employed for the breakdown withstanding structure.
Any of the breakdown withstanding structures described above, however, have realized only 90% of the ideal breakdown voltage calculated from the semiconductor substrate used and the breakdown withstanding structure employed. In order to realize the target breakdown voltage, it has been necessary to use a thick semiconductor substrate or to employ a breakdown withstanding structure having a sufficient leeway. Therefore, high on-resistance has inevitably been caused even in the semiconductor devices which require low on-resistance.
Only 90% of the ideal breakdown voltage has been realized due to the planar arrangement of the active region. Only 90% of the ideal breakdown voltage has been realized also due to the not fully optimized breakdown withstanding structure, which breaks down in advance to the active region. Each cause is explained in detail below.
First, the problem of the conventional active region is described. When the shape of p-type well region 13 is that shown in FIG. 37 or 38, the shape of each p-type well region 13 is defined by the surrounding n−-type surface regions 14 of n−-type drift layer 12. In other words, p-type well regions 13 are convex with respect to n−-type surface regions 14. Due to the convex shape of p-type well regions 13, the electric field strength across the pn-junction between p-type well region 13 and n−-type surface regions 14 is high due to the shape effect. Due to the high electric field strength, the breakdown voltage in the pn-junction region is lower than the breakdown voltage originally determined by the impurity concentrations in n−-type drift layer 12 and p-type well region 13. To avoid the problem described above, it has been necessary to dope n−-type drift layer 12 lightly. The lightly doped n−-type drift layer 12, however, causes high on-resistance.
To prevent the low breakdown voltage due to the shape effect of p-type well regions 13, U.S. Pat. No. 5,723,890 discloses a gate electrode, the main portion thereof is formed of a plurality of stripes extending in one direction. FIG. 39 is a top plan view showing the planar arrangement pattern of gate electrode 18 disclosed in U.S. Pat. No. 5,723,890. In FIG. 39, the main portion of p-type well region 13 is shaped with a stripe. Contact region 24 is shaped also with a stripe.
However, a MOSFET including stripes of gate electrode 18 is not always free from problems. The resistance of the gate electrode having square widows or hexagonal windows is suppressed at a low value, since the control signal flows through the gate electrode, which works like a network due the shape thereof. The resistance of the gate electrode formed of a plurality of stripes is as high as to cause the switching loss increase described later, since the control signal flows only in one direction from the ends of the stripes.
To reduce the loses of the MOSFET, it is necessary to reduce the switching loss as well as to reduce the loss caused by the on-resistance in the ON-state of the device. Generally described, for reducing the switching loss, it is important to shorten the switching time, especially the switching time, for which the device tuns from the ON-state to the OFF-state. For shorten the switching time of the vertical MOSFET, it is necessary to reduce the capacitance Crss between n−-type surface region 14 and gate electrode 18 facing n−-type surface region 14 across gate insulation film 17. For reducing the capacitance Crss, it is effective to narrow the width of n−-type surface region 14 between p-type well regions 13. However, the narrow width of n−-type surface region 14 between p-type well regions 13 causes a high resistance component due to the effect of the junction-type field-effect transistor (hereinafter referred to as “JFET resistance”), which is one of the on-resistance components of the MOSFET's. The high JFET resistance causes a high on-resistance.
U.S. Pat. No. 4,593,302 discloses a counter doping method, which obviates the problem of high JFET resistance. Although the counter doping technique facilitates suppressing the JFET resistance increase, the width of n−-type surface region 14 widened to reduce the JFET resistance causes lowering of the breakdown voltage. To avoid the lowering of the breakdown voltage, it is necessary to reduce the amount of the counter doped impurity. The reduced amount of the counter doped impurity is less effective to prevent the JFET resistance from increasing. Thus, any of the conventional techniques, which solves one problem, fails to another solve problem, as if going around in a circle without getting anywhere.
To reduce switching loss, it is effective to reduce the gate driving charge quantity Qg as well as to reduce the above described capacitance Crss. The gate driving charge quantity Qg is calculated by the following formula (1), which calculates the charge quantity, charged from 0 V to the driving voltage V1 (V) of the voltage between the gate and the source Vgs to the input capacitance Ciss of the MOS-type semiconductor device.                     Qg        =                              ∫            0                          V              ⁢                                                           ⁢              1                                ⁢                      Ciss            ×            Vgs            ⁢                                                   ⁢                                          ⅆ                C                            /                              ⅆ                V                                                                        (        1        )            Formula (1) indicates that the reduction of the input capacitance Ciss results in reduction of the gate driving charge quantity Qg.
The input capacitance Ciss of the MOS-type device is expressed by the following formula (2) including the capacitance between the terminals.
 Ciss=Cgs+Cgd  (2)
Here, Cgs is the capacitance between the gate and the source, and Cgd is the capacitance between the gate and the drain (that is Crss).
In addition to the foregoing JFET resistance reduction which employs counter doping, there is another conventional way of reducing the capacitance Crss. FIG. 40 is a cress sectional view of another conventional n-channel vertical MOSFET, which reduces the capacitance Crss. Referring now to FIG. 40, the n-channel vertical MOSFET includes a thick gate insulation film 25 disposed on a part of gate insulation film 17 facing n−-type surface region 14 to reduce the capacitance Crss. However, since steps are caused between the thick gate insulation films 25 and 17, the electric field strength in the step portions is high. The high electric field strength causes a low breakdown voltage. Although narrowing the area of gate electrode 18 may be effective to reduce the capacitance Cgs between the gate and the drain, the narrowed area, for example, of the stripe-shaped gate electrode shown in FIG. 39 increases the gate resistance inside the device, causing switching loss increase.
Now we consider the breakdown withstanding structure. Since the pn-junction between p-type well region 13 and n−-type drift layer 12 has a curvature in the outermost peripheral portion of the p-type well region 13 at the same potential with that of source electrode 19 on n−-type drift layer 12 as a breakdown-voltage sustaining layer, the electric field strength in the curved pn-junction rises more quickly than the electric field strength in the straight pn-junction. The electric field strength in the curved pn-junction reaches the critical electric field strength at a voltage lower than the breakdown voltage calculated from the structure of the breakdown-voltage sustaining layer, causing breakdown.
It would be desirable to provide a semiconductor device with a high breakdown voltage, which facilitates greatly reducing the tradeoff relation between the on-resistance and the breakdown voltage, and reducing both the on-resistance and the switching loss.